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HD-4702
Data Sheet August 24, 2006 FN2954.2
CMOS Programmable Bit Rate Generator
The HD-4702 Bit Rate Generator provides the necessary clock signals for digital data transmission systems, such as a UART. It generates 13 commonly used bit rates using an onchip crystal oscillator or an external input. For conventional operation generating 16 output clock pulses per bit period, the input clock frequency must be 2.4576MHz (i.e. 9600 Baud x 16 x 16, since there is an internal 16 prescaler). A lower input frequency will result in a proportionally lower output frequency. The HD-4702 can provide multi-channel operation with a minimum of external logic by having the clock frequency CO and the 8 prescaler outputs Q0, Q1, Q2 available externally. All signals have a 50% duty cycle except 1800 Baud, which has less than 0.39% distortion. The four rate select inputs (S0-S3) select which bit rate is at the output (Z). See Truth Table for Rate Select Inputs for select code and output bit rate. Two of the 16 select codes for the HD-4702 do not select an internally generated frequency, but select an input into which the user can feed either a different frequency, or a static level (High or Low) to generate "ZERO BAUD". The bit rates most commonly used in modern data terminals (110, 150, 300, 1200, 2400 Baud) require that no more than one input be grounded for the HD-4702, which is easily achieved with a single 5-position switch. The HD-4702 has an initialization circuit which generates a master reset for the scan counter. This signal is derived from a digital differentiator that senses the first high level on the CP input after the ECP input goes low. When ECP is high, selecting the crystal input, CP must be low. A high level on CP would apply a continuous reset. See Clock Modes and Initialization below.
Features
* HD-4702 Provides 13 Commonly Used Bit Rates * Uses a 2.4576MHz Crystal/Input for Standard Frequency Output (16 Times Bit Rate) * Low Power Dissipation * Conforms to EIA RS-404 * One HD-4702 Controls up to Eight Transmission Channels * Initialization Circuit Facilitates Diagnostic Fault Isolation * On-Chip Input Pull-Up Circuit
Ordering Information
PACKAGE PDIP PDIP (Pb-free) CerDIP SMD# TEMP. RANGE (oC) PART NUMBER PART MARKING HD3-4702-9 HD3-4702-9Z PKG. NO. E16.3 E16.3 F16.3
-40 to +85 HD3-4702-9 -40 to +85 HD3-4702-9Z*
-55 to +125 5962-9051801MEA
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
Truth Table
TRUTH TABLE FOR RATE SELECT INPUTS (Using 2.4576MHz Crystal) S3 L L L L L L L L H H H H H H H H S2 L L L L H H H H L L L L H H H H S1 L L H H L L H H L L H H L L H H S0 L H L H L H L H L H L H L H L H OUTPUT RATE (Z) MUX Input (IM) MUX Input (IM) 50 Baud 75 Baud 134.5 Baud 200 Baud 600 Baud 2400 Baud 9600 Baud 4800 Baud 1800 Baud 1200 Baud 2400 Baud 300 Baud 150 Baud 110 Baud
Pinout
HD-4702 (16 Ld PDIP) TOP VIEW
Q0 1 Q1 2 Q2 3 ECP 4 CP 5 OX 6 IX 7 GND 8 16 VCC 15 IM 14 S0 13 S1 12 S2 11 S3 10 Z 9 CO
NOTE: 19200 Baud by connecting Q2 to IM.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
HD-4702 Pin Description
PIN NUMBER 16 TYPE SYMBOL VCC GND I I CP ECP IX OX IM S0 - S3 CO Q 0 - Q2 Z DESCRIPTION VCC: Is the +5V power supply pin. A 0.1F capacitor between pins 16 and 8 is recommended for decoupling. GROUND EXTERNAL CLOCK INPUT EXTERNAL CLOCK ENABLE: A low signal on this input allows the baud rate to be generated from the CP input. CRYSTAL INPUT CRYSTAL DRIVE OUTPUT MULTIPLEXED INPUT BAUD RATE SELECT INPUTS CLOCK OUTPUT SCAN COUNTER OUTPUTS BIT RATE OUTPUT
8 5 4
7 6 15 11, 12, 13, 14 9 1, 2, 3 10
I O I I O O O
CLOCK MODES AND INITIALIZATION IX ECP H X X X L H L H CP L OPERATION Clocked from IX Clocked from CP Continuous Reset Reset During 1st CP = High Time
H = HIGH Level L = LOW Level X = Don't Care = Clock Pulse = 1st HIGH Level Clock Pulse after ECP goes LOW NOTE: Actual output frequency is 16 times the indicated Output Rate, assuming a clock frequency of 2.4576MHz.
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FN2954.2 August 24, 2006
Block Diagram
(NOTE) OSCILLATOR CIRCUIT SCAN COUNTER 15 14 13 12 11 IM S0 S1 S2 S3 9600 4800 2400 1200 600 300 150 75 CP MR CP MR 0 CP 2 3 Q MR 4 5 CP 75 134.5 200 6 7 8 MR 9 CP Q / 16/3MR 4800 10 1800 11 1200 12 2400 13 300 CO 9 1 2 3 Q0 Q1 Q2 CP 14 150 600 2400 9600 D Q CP 50 COUNTER NETWORK
MULTIPLEXER
7
IX
/
8
6
OX
3
/
4 Q MR 1
4
ECP
5
CP
/ 18
D FF CP Q MR 6 Q MR
Q
/
10 Z FF CP MR
HD-4702
INITIALIZATION CIRCUIT
/
22
Q MR
15 110
VDD = PIN 16 VSS = PIN 8 = PIN NUMBER
NOTE: See Figure 4 in Design Information for Crystal Specifications.
FN2954.2 August 24, 2006
HD-4702 Application Information
Single Channel Bit Rate Generator Figure 1 shows the simplest application of the HD-4702. This circuit generates one of five possible bit rates as determined by the setting of a single pole, 5-position switch. The Bit Rate Output (Z) drives one standard TTL load or four low power Schottky loads over the full temperature range. The possible output frequencies correspond to 110, 150, 300, 1200, and 2400 Baud. For many low cost terminals, these five bit rates are adequate.
1 2 3 IM CP 56pF 56pF 10M 2.4576 MHz CRYSTAL OUTPUT ECP HD-4702 S0 S1 4 S2 S3 A0 D E 93L34 A1 A2 CL Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 300 4800 1800 1200 9600 2400 150 S2 S3 Q2 Z 110 SPST SWITCH 5
Other bit rate combinations can be generated by changing the Scan Counter to Selector interconnection or by inserting logic gates into this path.
IM CP 56pF 56pF 10M 2.4576 MHz CRYSTAL ECP
S0
S1
S2
S3
HD-4702
IX OX CO Q0 Q1 Q2 Z
IX OX CO Q0 Q1 Q2 Z
See Table 1.
FIGURE 2. BIT RATE GENERATOR CONFIGURATION WITH EIGHT SIMULTANEOUS FREQUENCIES
See Table 1.
19200 Baud Operation
SWITCH POSITION 1 2 3 4 5 HD-4702 BIT RATE 110 Baud 150 Baud 300 Baud 1200 Baud 2400 Baud
Though a 19200 Baud signal is not internally routed to the multiplexer, the HD-4702 can be used to generate this bit rate by connecting the Q2 output to IM input and applying select code. An additional 2-input NOR gate can be used to retain the "Zero Baud" feature on select code 1 for the HD-4702 (See Figure 3).
FIGURE 1. SWITCH SELECTABLE BIT RATE GENERATOR CONFIGURATION PROVIDING FIVE BIT RATES
IM CP 56pF 56pF 10M 2.4576 MHz CRYSTAL ECP
S0
S1
Simultaneous Generation of Several Bit Rates Figure 2 shows a simple scheme that generates eight bit rates on eight output lines, using one HD-4702 and one 93L34 Bit Addressable Latch. This and the following applications take advantage of the built-in scan counter (prescaler) outputs. As shown in the block diagram, these outputs (Q0 to Q2) go through a complete sequence of eight states for every halfperiod of the highest output frequency (9600 Baud). Feeding these Scan Counter Outputs back to the Select Inputs of the multiplexer causes the HD-4702 to interrogate sequentially eight different frequency signals. The 93L34 8-bit addressable Latch, addressed by the same Scan Counter Outputs, re-converts the multiplexed single Output (Z) of the HD-4702 into eight parallel output frequency signals. In the simple scheme of Figure 2, input S3 is left open (HIGH) and the following bit rates are generated:
Q0: 110 Baud Q3: 1800 Baud Q6: 300 Baud Q1: 9600 Baud Q4: 1200 Baud Q7: 150 Baud Q2: 4800 Baud Q5: 2400 Baud
HD-4702
IX OX CO Q0 Q1
OUTPUT
See Table 1.
FIGURE 3. 19200 BAUD OPERATION TABLE 1. CRYSTAL SPECIFICATIONS PARAMETERS Frequency Series Resistance (Max) Unwanted Modes Type of Operation Load Capacitance TYPICAL CRYSTAL SPEC 2.4576MHz "AT" Cut 250 -6.0dB (Min) Parallel 32pF +0.5
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FN2954.2 August 24, 2006
HD-4702
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Typical Derating Factor . . . . . . . . . . . 1mA/MHz Increase in ICCOP
Thermal Information
Thermal Resistance (Typical) CERDIP Package. . . . . . . . . . . . . . . PDIP Package . . . . . . . . . . . . . . . . . JA 78oC/W 90oC/W JC 23oC/W N/A
Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Maximum Junction Temperature Ceramic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . .+300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .720 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range HD-4702-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC HD-4702-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Electrical Specifications
VCC = 5V 10%, TA = -40oC to +85oC (HD-4702-9), TA = -55oC to +125oC (HD-4702-8) LIMITS
SYMBOL VIH VIL VOH1 VOL1 IIH IILX IIL IOHX IOH1 IOH2 IOLX IOL ICC
PARAMETER Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input High Current Input Low Current (lX Input) Input Low Current (All Other Inputs) Output High Current (OX) Output High Current (All Other Outputs) Output High Current (All Other Outputs) Output Low Current (OX) Output Low Current (All Other Outputs) Supply Current (Static)
MIN VCC 70% VCC -0.1 -1 -1 -0.1 -1.0 -0.3 0.1 1.6 -
MAX VCC 30% 0.1 +1 +1 -100 1500 1000
UNITS V V V V A A A mA mA mA mA mA A A VCC = 4.5V VCC = 4.5V
TEST CONDITIONS
IOH -1A, VCC = 4.5V, (Note 1) IOL +1A, VCC = 4.5V, (Note 1) VIN = VCC, All 0ther Pins = 0V, VCC = 5.5V VIN = 0V, All Other Pins = VCC, VCC = 5.5V VIN = 0V, All Other Pins = VCC, VCC = 5.5V (Note 2) VOUT = VCC - 0.5, VCC = 4.5V, Input at 0V or VCC per Logic Function or Truth Table VOUT = 2.5V, VCC = 4.5V, Input at 0V or VCC per Logic Function or Truth Table VOUT = VCC -0.5, VCC = 4.5V, Input at 0V or VCC per Logic Function or Truth Table VOUT = 0.4V, VCC = 4.5V, Input at 0V or VCC per Logic Function or Truth Table VOUT = 0.4V, VCC = 4.5V Input, at 0V or VCC per Logic Function or Truth Table ECP = VCC, CP = 0V, VCC = 5.5V, All Other Inputs = GND, (Note 2) ECP = VCC, CP = 0V, VCC = 5.5V, All Other Inputs = VCC, (Note 2)
NOTES: 1. Interchanging of force and sense conditions is permitted. 2. Input Current and Quiescent Power Supply Current are relatively higher for this device because of active pull-up circuits on all inputs except IX.
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FN2954.2 August 24, 2006
HD-4702
Electrical Specifications
VCC = 5V 10%, TA = -40oC to +85oC (HD-4702-9), TA = -55oC to +125oC (HD-4702-8) LIMITS SYMBOL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL ts th ts th twCP(L) twCP(H) twCP(L) twCP(H) tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL NOTES: 1. Propagation Delays (tPLH and tPHL) and Output Transition Times (tTLH and tTHL) will change with Output Load Capacitance (CL). Setup Times (ts), Hold Times (th), and Minimum Pulse Widths (tw) do not vary with load capacitance. 2. For multichannel operation, Propagation Delay (CO to Qn) plus Set-Up Time, Select to CO, is guaranteed to be 367ns. 3. The first High Level Clock Pulse after ECP goes Low must be at least 350ns long to guarantee reset of all Counters. 4. It is recommended that input rise and fall times to the clock inputs (CP, IX) be less than 15ns. Output Transition Time (Except OX) Propagation Delay CO to Z Propagation Delay CO to Qn Propagation Delay CP to CO Set-Up Time, Select to CO Hold Time, Select to CO Set-Up Time, IM to CO Hold Time, IM to CO Minimum Clock Pulse Width, Low (Notes 3, 4) Minimum Clock Pulse Width, High (Notes 3, 4) Minimum IX Pulse Width, Low (Note 4) Minimum IX Pulse Width, High (Note 4) Propagation Delay IX to CO Output Transition Time (Except OX) Propagation Delay, CO to Z Propagation Delay, CO to Qn Propagation Delay, CP to CO AC PARAMETER Propagation Delay, IX to CO MIN 350 0 350 0 120 120 160 160 MAX 350 275 260 220 (Note 2) (Note 2) 85 75 160 75 300 250 215 195 (Note 2) (Note 2) 75 65 80 40 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns VCC = 4.5V CL 7pF on OX CL = 15pF (Note 1) VCC = 4.5V CL 7pF on OX CL = 50pF (Note 1) TEST CONDITIONS
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FN2954.2 August 24, 2006
HD-4702
Capacitance
SYMBOL CIN COUT TA = +25oC; Frequency = 1MHz PARAMETER Input Capacitance Output Capacitance TYPICAL 7 15 UNITS pF pF CONDITIONS All measurements are referenced the device GND
Switching Waveforms
tW(H) 50% CP/IX 50% tW(L) 50%
50% CO
ts IM/SN 50%
th
NOTE: 1. Setup and Hold times are shown as positive values but may be specified as negative values.
AC Testing Input, Output Waveform
INPUT VIH VIL 50% OUTPUT VOH 50% VOL
NOTE: 1. AC Testing: All input signals must switch between VIL and VIH. Input rise and fall times are driven at 1ns per volt.
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FN2954.2 August 24, 2006
HD-4702 Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240
MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280
A
E A2 L A C L
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1
A1 A2
-C-
B B1 C D D1 E
eA eC
C
e
C A BS
eB
NOTES: 2. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 3. Dimensioning and tolerancing per ANSI Y14.5M-1982. 4. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 5. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 6. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 7. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 8. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 9. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 10. N is the maximum number of terminal positions. 11. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
E1 e eA eB L N
0.100 BSC 0.300 BSC 0.115 16 0.430 0.150
2.54 BSC 7.62 BSC 2.93 16 10.92 3.81
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FN2954.2 August 24, 2006

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